Give yourself a head-start with optimum JTAG signal termination

Even relatively the slow clocks (<10MHz) associated with JTAG signalling often have fast edges and should be terminated correctly to avoid ringing and the possibility of double clocking. By designing your circuit with a suitable R-C termination close to the end of the TCK line you can eliminate many of these issues. Try a 100pF and 75 Ohm resistor in series to ground as a starting point, then adjust the values to give an optimum looking clock.

If you have a large number of parts (e.g. >6) on a single scan chain then buffering the parallel signals TMS and TCK can help overcome fan-out issues. A series resistor close to the last device TDO pin also helps to damp reflections from the TDO (return) signal.

The diagram below summarises the suggested signal terminations.

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