With newer designs we are finding that the hardware is available much quicker than the firmware, thus the hardware design teams are unable to prove/debug their peripheral circuits and manufacturing need to ensure correct placement of components, as soon as possible. Due to my experience on JTAG, I was asked to provide a simple, low cost, low complexity solution.

The design in question contained two FPGA’s: EPM240T and a LC4512V in a single TAP chain. The board contained around 50 device ‘clusters’ either controlled or monitored by either or both of the FPGA’s. We already owned several JT 3705/USB boundary-scan controllers for training, proving and production solutions, so it was an easy decision to use one in conjunction with JTAG Live Buzz to debug the hardware. Suitable break-out boxes/leads were used to allow power, stimulus and monitoring of the boards IO.

JTAG Live was loaded onto a standalone laptop and the JT 3705-USB controller connected and the Buzz application configured to use this device. The two BSDL files where uploaded from the manufacturers web-site. We followed the instructions and within 5 mins we were able to confirm the (scan-path) infrastructure of the board, confirming the functionality of the JTAG boundary scan chain. (The Buzz demo video on the JTAG Live webpage was very helpful).

Using the ‘Buzz’, and for some lines the ‘Measure’ window, all interconnects between the FPGA’s were tested, driving outputs high and low and ensuring the corresponding inputs follow. We then used the ‘Watch’ window to check that all the free running clocks were running, indicated by the logic value in the ‘Value’ window alternating from a 0/1. It was then a matter of running through all the FPGA inputs (using the circuit diagram for reference) and stimulating the CCA inputs and checking that the ‘Values’ change from one state to the next. A similar exercise was then performed on the CCA outputs/ FPGA outputs, this was done using the ‘Buzz’ window with an oscilloscope connected. The ‘Constraints’ window was used to allow enabling of buffers; after firstly proving the buffer EN circuit utilising the ‘Measure’ window. This speeded up testing considerably.

Conclusion

Using JTAG Live and ~ £800 of JTAG controller hardware we were able, over two days, to prove the manufacture and electronic integrity of a new hardware design.